New Electronic Materials for Extending Moore’s Law:
Stacey
F. Bent
Kyeongjae
Cho
Jeffrey Gambino
Paul
McIntyre
John
Mardinly
Charles
Musgrave
Yoshio
Nishi
Krishna
Saraswat
Sadasivan
Shankar
Robert
Sinclair
David
Taylor
Stacey F. Bent is Associate
Professor of Chemical Engineering at Stanford University. She received her
B.S. degree in chemical engineering from the University of California,
Berkeley in 1987, and her Ph.D. in chemistry from Stanford University in
1992. In 1992, Bent joined AT&T Bell Laboratories as a postdoctoral
fellow, and from 1994 to 1998 was Assistant Professor of Chemistry at New
York University. In 1998, Bent moved to Stanford University. In addition
to her appointment in Chemical Engineering, she is also an Associate
Professor, by courtesy, in the Departments of Chemistry, Materials Science
and Engineering, and Electrical Engineering.
Prof. Bent's research activities focus on electronic materials processing and surface chemistry. Her research group is currently exploring new approaches for surface functionalization, methods for area selective film deposition, studies of organic electronic materials, and surface patterning for control of cell growth for retinal prostheses.
Bent is the recipient of the CAREER Award from the National Science Foundation, the Peter Mark Award from the American Vacuum Society, and the Coblentz Award for molecular spectroscopy. She has also been named a Beckman Young Investigator, a Camille Dreyfus Teacher-Scholar, and a Cottrell Scholar.
To TopKyeongjae Cho is Assistant Professor of Mechanical Engineering and (by courtesy) of Materials Science and Engineering. Prof. Cho earned a Ph.D. in Physics from MIT in 1994. He is a Fellow of the Institute of Physics (since 2002) and has received the Veridian Outstanding Technical Authors Award (2000), a Frederich E. Terman Fellowship (1997-2000), a MIT Industry Liaison Fellowship (1988), and a Korean Government Overseas Study Fellowship (1988-1990). He is on the Editorial Board of Modeling and Simulation in Materials Science and Engineering.
Kyeongjae (KJ) Cho's research area is computational materials modeling using high-performance supercomputers. To investigate complex materials properties with true predictive power, his group is applying efficient atomistic simulation programs which enable one to study increasingly larger complex materials systems with more accuracy. The complex materials systems he has studied using the atomistic method encompass a wide range of different nanomaterial systems, biomolecules, and electronic materials.
Jeffrey Gambino received the B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and the Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices. In 1992, he joined the DRAM development alliance at IBM's Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-mm DRAM products. In 1999, he joined IBM's manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic technology. He has published over 90 technical papers and holds over 100 patents.
Paul C. McIntyre is Associate Professor of Materials Science and Engineering and a member of the Geballe Laboratory for Advanced Materials at Stanford University . He is an internationally recognized expert in high permittivity dielectrics, deposition of ultrathin metal oxide films, and metal oxide/semiconductor interface structures and properties. His research group receives annual financial support from several US government agencies and numerous major semiconductor corporations to perform work on these and related topics. Prior to joining the faculty of Stanford University in 1997, McIntyre was a member of the technical staff in the Semiconductor R&D division at Texas Instruments in Dallas , TX . He was previously a Director's Fund Postdoctoral Fellow in the Materials Science and Technology division of Los Alamos National Laboratory. McIntyre obtained his Doctor of Science degree from the Materials Science and Engineering department at MIT in 1993. He is the author or coauthor of approximately 70 archival journal articles and an inventor of four issued patents. McIntyre is a recipient of an IBM Faculty Award and Powell Foundation Fellowship in support of his research at Stanford.
Dr. John Mardinly received a BS in Engineering Physics, and BS, MS and Ph.D. in Metallurgical Engineering at the University of Michigan. He worked in the Metallurgical Research group at Northrop Aircraft for one year, and then in the materials laboratories at Lockheed Missiles and Space Company for eight years. In 1992, he joined the Materials Technology group at Intel Corporation in Santa Clara, leading the Transmission Electron Microscopy Group, and has published numerous papers describing the application of TEM to microelectronic device problems, and technological barriers to the preparation of TEM samples of device features with a size approaching the mean free path of electrons in silicon.
Charles Musgrave is Assistant Professor of Chemical Engineering and (jointly) of Materials Science and Engineering at Stanford University . He earned a B.S. degree in Materials Science from UC Berkeley in 1988 and M.S. (1990) and Ph.D. (1994) from CalTech. Since 1996, Prof. Musgrave has been a faculty member at Stanford. Prior to this, he was a postdoctoral research scientist in the Department of Chemical Engineering at MIT. Musgrave is an expert in first principles simulations of surface reactions and interface processes, with emphasis on materials that are of interest in semiconductor device fabrication. He is an author of approximately 60 publications on these topics. Musgrave is a recipient of the AIChE NorCal Award for Academic Teaching, a Charles Lee Powell Foundation Fellowship, and the 1 st Feynman Prize in Nanotechnology.
Yoshio Nishi received his BS in Material Science and PhD in Electronics Engineering from Waseda University in 1962 and the University Tokyo in 1973, respectively. He joined Toshiba R&D, Japan, in 1962 in the areas of research for semiconductor device physics and interfaces, mostly in silicon, resulting in discovery of ESR P B Center at the SiO 2 -Si interface, and development of the first 256 bit MNOS non-volatile RAM, of the SOS 16 bit micro-processor and the world's 1 st 1 Mb CMOS DRAM. He joined Hewlett-Packard (1986) as the Director of the Silicon Process Lab, followed by establishing the ULSI Research Lab as its Founding Director. He joined Texas Instruments, Inc.(1995) as Senior VP and Director of Research and Development for the Semiconductor Group where he implemented a new R&D model for silicon technology development by establishing the Kilby Center . Since May 2002, Prof. Nishi has been a faculty member in the Electrical Engineering department at Stanford University . He has published more than 120 papers including conference proceedings, and co-authored 7 books. He holds more than 70 patents in the US and Japan . Prof. Nishi has served SRC and International Sematech as a Board member, NNI Panelist, MARCO Governing Council member, etc. He has been a Fellow of IEEE since 1987, and was recipient of the 1995 IEEE Jack Morton Award, and the 2002 Robert Noyce Medal.
Krishna Saraswat is Rickey/Nielsen Professor of Engineering and Professor of Electrical Engineering at Stanford University . He received his B.E. degree in Electronics in 1968 from the Birla Institute of Technology and Science, Pilani , India , and his M.S. and Ph.D. degrees in Electrical Engineering in 1969 and 1974 respectively from Stanford University , Stanford , CA . During 1969-70, he worked on microwave transistors at Texas Instruments. Returning to Stanford in 1971, he did his Ph.D. on high voltage MOS devices and circuits. After graduating he joined Stanford University as a Research Associate in 1975 and became a Professor of Electrical Engineering in 1983. He pioneered the technologies for aluminum/titanium layered interconnects, CVD of tungsten silicide MOS gates, CVD tungsten MOS gates and tunable workfunction SiGe MOS gates. During the late 80's he became interested in the economics and technology of single wafer manufacturing. He developed equipment and simulators for single wafer thermal processing, deposition and etching and technology for the in-situ measurements and real-time control. Jointly with Texas Instruments a microfactory for single wafer manufacturing was demonstrated in 1993. Since the mid 90's Prof. Saraswat has been working on new materials, devices and interconnects for scaling MOS technology to nm range. He has pioneered several new concepts of 3-D ICs with multiple layers of heterogeneous devices. His group has recently demonstrated the first high performance germanium MOSFETs with high- k dielectrics. Since 2000 he has also been doing research on Environmentally Benign Semiconductor Manufacturing and is currently Associate Director of the NSF/SRC Engineering Research Center on this topic.
Saraswat has authored or co-authored over 400 technical papers, of which six have received Best Paper Awards . He is a Fellow of the IEEE. He received the Thomas Callinan Award from The Electrochemical Society in 2000 for his contributions to the dielectric science and technology. Saraswat is the recipient of the 2004 IEEE Andrew Grove Award for seminal contributions to silicon process technology.
Dr. Sadasivan Shankar is a Senior Principal Engineer in Logic Technology Development and currently manages Integrated Processing Applications in Technology CAD, Intel Corporation. His group is chartered with development and application of Materials and processing modeling in Technology and Manufacturing Group. He received a Ph.D in Chemical Engineering and Material Science from University of Minnesota, Minneapolis in 1991 for Large-scale Modeling of Glow discharges for Plasma processing of Semiconductors. Since joining Intel, Dr. Shankar has worked on models for plasma physics, chemistry, Monte Carlo simulation of three dimensional flows, gas and surface reactions, wafer scale-up, multi-scale analysis, algorithm development for low pressure chemical vapor deposition systems, electroplating, chemical mechanical planarization, electromigration and stress, crack propagation and effluent treatment.
Dr. Shankar is involved in the SRC on the Technical Advisory Board for Backend Processing. He is also involved in the Sematech projects on plasma. He is a member of 2003 American Vacuum Society national meeting planning committee and was also on a NSF Review panel. He was a recipient of departmental fellowship for doctoral study and a NSF advanced Scientific Computing Post-doctoral Research Associateship and National Merit Scholarship from the Indian Government. His group works with several universities in and outside US, to co-develop models and methodologies for application to Intel are leading edge ULSI processes. He has been an Intel Distinguished lecturer in Universities, co-author of several contributed and invited papers and book chapters, on time and length scales in plasma etching, low pressure chemical vapor deposition, process equipment modeling (plasma, CMP, Electrodeposition), ultra low pressure three dimensional neutral flow, multi-scale modeling and on the history of thermodynamics.
Robert Sinclair has spent over 30 years developing and applying characterization techniques (such as high-resolution and in situ TEM) to materials and interface studies, particularly in the semiconductor field. He was educated at Cambridge University in materials science, spent postdoctoral positions at Newcastle and Berkeley and has been on the Stanford faculty since 1977. He has also had several visiting scientist positions, including appointments in Grenoble and at Matsushita Electric, Osaka . He has over 165 refereed publications, several edited works, book chapters and patents, and is currently Chair of the Department of Materials Science and Engineering, Director of the Stanford Nanocharacterization Laboratory and Chair of the National Research Council's Committee on Smaller Facilities.
David V. Taylor is a Postdoctoral Research Scholar in the Department of Materials Science and Engineering at Stanford University . His research interests include novel materials for nonvolatile memory applications as well as growth and transport properties of germanium nanowires. In 1999, he received his Ph.D. from the department of Materials Science at the Swiss Federal Institute of Technology in Lausanne (EPFL), Switzerland . His work focused on the dielectric, piezoelectric and ferroelectric properties of Pb(Zr,Ti)O 3 thin films. In 2000, he joined the department of Materials Science and Engineering of the University of California , Berkeley , as a Research Fellow. He was involved in the fabrication and driving conditions of flexural displacement actuators for the Micromechanical Flying Insect project. In 2001, he joined the Electronics Research Laboratory at Agilent Laboratories in Palo Alto , CA , as an R&D engineer. He was the lead electrical test engineer on a joint development project with Texas Instruments (TI) to fabricate embedded FeRAMs using TI's state-of-the-art 0.13 m m CMOS logic process.
