New Electronic Materials for Extending Moore's Law

The Institute online program on New Electronic Materials for Extending Moore's Law explores new materials for continuing the dimensional scaling of MOS devices with emphasis on the selection criteria, prototyping, compatibility and reliability of innovative solutions.  This online program offers a series of eight short courses by Stanford faculty as well as leading experts from other universities and industry.

• Advances in Computational Prototyping of Electronic Materials
• Atomic Layer Deposition of High-k Dielectrics: Substrate Preparation, Precursor Selection, and Process Conditions
• Future Device Requirements for High Performance MOSFETs
• Low-k Dielectrics: Requirements, Materials Options, and Integration
• Materials for New High-Density Nonvolatile Memories
• Materials Selection and Performance of High-k Gate Dielectrics
• Metal Gate Electrodes and Advanced Source/Drain Contacts for Future Transistors
• Nano Characterization for Research, Development and Failure Analysis in Electronics
  

Advances in Computational Prototyping of Electronic Materials
Prof. Kyeongjae Cho, Department of Mechanical Engineering, Stanford University Dr. Sadasivan Shankar, Intel Corporation, Santa Clara, CA

Computational prototyping of materials enables development of optimized scaled devices using new materials. This course presents the hierarchical multiscale modeling methods, which can connect device & process modeling tools to microscopic material modeling methods. These methods provide atomic structure optimization, and determine the corresponding electronic structures. These microscopic materials properties provide input data for device modeling tools for computational prototyping of the devices. We provide a general framework of multiscale modeling and make practical links to scaled device applications.
(204 minutes)

Atomic Layer Deposition of High-k Dielectrics: Substrate Preparation, Precursor Selection, and Process Conditions
Prof. Charles Musgrave, Departments of Chemical Engineering and Materials Science and Engineering, Stanford University,
Prof. Stacey F. Bent, Department of Chemical Engineering, Stanford University.

This course provides a mechanistic view of the ALD process chemistry for understanding the ALD characteristics and for developing new ALD processes. We present the ALD techniques and chemical mechanisms for various precursors and processes. We describe the impact of the high-k interface on electrical properties, along with various surface preparation techniques used for controlling the interfacial properties. The implications of substrate preparation, precursor selection, and reaction mechanisms on the ALD processes are examined.
(206 minutes)

Future Device Requirements for High Performance MOSFETs
Prof. Krishna C. Saraswat, Department of Electrical Engineering, Stanford University

As the scaling of bulk CMOS reaches its limits in the sub-20nm regime, new devices and materials will be required to continue the historic scaling trends. This course presents the future MOSFET requirements and solutions. The course covers double-gate or surround-gate MOS devices, Ge-nanowire & carbon-nanotube high-mobility channels, high-k dielectrics, and metal gates. Si-based devices using these materials may enable sub-10 nm technologies, but will require processes compatible with mainstream manufacturing.
(193 minutes)

Low-k Dielectrics: Requirements, Materials Options, and Integration
Dr. Jeff Gambino, IBM

This course describes the properties and processing of low-k materials.We present the materials options and the thermal, chemical, and mechanical properties of low-k materials.The materials options include organic versus inorganic dielectrics, dense versus porous dielectrics, and CVD versus spin-on films. Dielectrics for etch-stop and capping layers as well as process integration of low-k and copper are discussed.The course reviews the reliability issues of low-k dielectrics, including electromigration, stress migration, thermal failures, moisture absorption, and packaging problems.
(239 minutes)

Materials for New High-Density Nonvolatile Memories
Dr. David Taylor, Department of Materials Science and Engineering, Stanford University

The use of nonvolatile memory is a key enabler for mobile electronics. This course reviews fairly mature and developing materials candidates for the next generation of low-power, fast access time, high-density nonvolatile embedded memory. We examine the memory materials and cells of Ferroelectric Random Access Memory (FeRAM), Magnetoresistive RAM (MRAM), Ovonics Unified Memory or Phase-Change RAM (OUM / PRAM), and Polymer Memory. Memory operating principles, performance, materials selection, processing and integration issues, and structure-property relations are reviewed.
(187 minutes)

Materials Selection and Performance of High-k Gate Dielectrics
Prof. Paul C. McIntyre, Department of Materials Science and Engineering, Stanford University

This course reviews MOS performance & stability requirements and the high-k dielectrics which meet them. It reviews deposition of alternative gate dielectrics by CVD, ALD, and physical vapor deposition methods. The effects of dielectric microstructure, interface states and the phonon properties of high-k materials in controlling key MOS electrical characteristics are described. The course addresses compatibility of high-k dielectrics with various gate metals and novel semiconductor substrates, reliability of high-k gates, and prospects for "ultrahigh" dielectric materials (k > 50).
(193 minutes)

Metal Gate Electrodes and Advanced Source/Drain Contacts for Future Transistors
Professor Yoshio Nishi, Department of Electrical Engineering, Stanford University

As we approach the simple scaling limit of polysilicon gate transistors, alternative technologies such as metal gates, ultra-shallow junctions and metal Schottky junctions for source and drain have become critical for further extension of CMOS. This course examines how far we can go with simple scaling, and describe the state-of-the-art metal gate and novel source/drain engineering. We examine novel materials solutions that involve the control of the electronic structure at materials interfaces in future transistors.
(213 minutes)

Nano Characterization for Research, Development and Failure Analysis in Electronics
Prof. Robert Sinclair, Department of Materials Science and Engineering, Stanford University, Dr. John Mardinly, Intel Corp., Santa Clara, CA

This course covers the applications of modern materials characterization methods to studying nano-scale structures, for R&D, manufacturing, and failure analysis of microelectronic components. The modern characterization lab is equipped with high-resolution microscopes and surface analysis instruments. This course reviews recent and applications, especially as they relate to the nano-scale. Examples of various analytical techniques (SEM, FIB, TEM, nano-Auger, nano-SIMS, XPS, etc.), as applied to current and future microelectronics, are presented.
(193 minutes)