Semiconductor Devices & Manufacturing
Dennis
Buss
Jean-Pierre
Colinge
David
Goldhaber-Gordon
David
Harame
Paul Kohl
Yoshio
Nishi
Fabian Pease
T.J.
Rodgers
Krishna
Saraswat
Robert Socha
Dr. Dennis D. Buss, Ph.D., Vice President, Si Technology Development, Texas Instruments Incorporated. Dr. Buss is Vice President of Silicon Technology Development at Texas Instruments Incorporated with responsibility for Technology Computer Aided Design (TCAD) and is the chairman of TI’s Technical Ladder Policy Board (TLPB).
Dennis began his industrial career at Texas Instruments in July 1969. During the next 18 years, Dennis was TI Fellow and later Vice President and Director of TI's Semiconductor Process and Design Center.
Between 1987 and 1997, Dennis was Vice President of Technology at Analog Devices. He returned to Texas Instruments in December 1997.
Dennis received his BS, MS and Ph.D. in Electrical Engineering from MIT in 1963, 1965 and 1968. He served twice on the Electrical Engineering faculty at MIT in 1968-1969 and 1974-1975. He is an IEEE Fellow and the recipient of the 1985 Herschel Award and the 1987 Jack A. Morton Award for his pioneering work on HgCdTe Infra-Red monolithic focal plane technology. In February 2000, Dennis was selected by the Electron Devices Society to be one of the recipients of an IEEE Third Millennium Medal.
Jean-Pierre Colinge, Ph.D.,
Professor of Electrical Engineering, University of California,
Davis.
Dr. Jean-Pierre Colinge is professor of electrical Engineering
at the University of California, Davis. He received a BS degree in
Philosophy, the Electrical Engineer degree, and the Ph.D. degree in
Applied Sciences from the Université Catholique de Louvain,
Louvain-la-Neuve, Belgium, in 1980, 1980, and 1984, respectively.
From 1981 to 1984 he was Researcher at the Centre National d'Etudes des Télécommunications (CNET), Grenoble, France, where he developed early for the fabrication of SOI films and developed the "Stacked CMOS" technique (one of the first 3D structures). From 1985 to 1988 he was member technical staff of the Hewlett-Packard Research Labs, Palo Alto, CA, where he carried out research and development work on thin-film SOI devices and discovered many of the properties of fully depleted SOI devices (sharp subthreshold slope, absence of kink effect, properties of transconductance, etc.) From 1988 to 1991 he was project leader for the SOI research at IMEC (Inter University Microelectronics Center) in Leuven, Belgium. He designed and fabricated novel SOI devices, including radiation-hard devices and the first double-gate SOI transistors. From 1991 to 1997 he was Professor at the Université Catholique de Louvain, heading research in the areas of SOI device physics and technology, high-temperature SOI integrated circuits, radiation-hard integrated SOI circuits, quantum effects (2D,1D) in SOI devices, microwave SOI devices, and low-power SOI circuits. He is currently carrying research in advances multiple-gate SOI MOSFET device physics.
He has been on the committee of several conferences, including IEDM and SSDM, has been General Chairman of the IEEE SOS/SOI Technology Conference in 1988, and is a Fellow of IEEE. He has published over 250 scientific papers and three books on the field of SOI as well as two books on semiconductor device physics and four book chapters on SOI. Dr. Colinge has given lectures on SOI at short courses offered by various conferences, including IEDM, NSREC and the IEEE International SOI Conference.
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David Goldhaber-Gordon, Ph.D.,
Assistant Professor, Physics, Stanford University.
Prof. David
Goldhaber-Gordon’s experimental research group studies how electrons in
semiconductors behave when they are confined to small "boxes", restricted
to discrete quantum states in one, two, or even all three spatial
dimensions. This emerging field of enquiry is called mesoscopic physics,
as it explores length scales around 100 nanometers, between the
microscopic size of atoms and the macroscopic scale of
conveniently-grasped everyday objects.
Over the last decade, mesoscopic physics has forced us to grapple with new ways of thinking about quantum mechanics, especially for systems of interacting particles. Current CMOS transistors are now in this same size range, so some of the same considerations are becoming important in device design.
Prof. Goldhaber-Gordon maintains an active interest in nanoelectronic computing, and wrote a seminal paper on the subject in 1997. He is the recipient of a 1998 Award for Best Paper by a Young Author at the International Conference on Physics of Semiconductors, as well as the 2002 George E. Valley Prize of the American Physical Society, the 2002 MacMillan Award of the University of Illinois, and a 2003 Sloan Fellowship.
David Harame, Ph.D., Director
Semiconductor Technologies Enablement, IBM.
David Harame received the
PhD in Electrical Engineering from Stanford University in 1984. He joined
IBM in 1984 at the T.J. Watson Research Center in Yorktown Heights NY
where he immediately began working on using epitaxial growth techniques in
silicon technology to improve device performance. He worked on both SiGe
HBTs and SiGe Channel FETs. Dr. Harame was involved with the SiGe HBT work
at IBM from its inception and is widely credited for taking the technology
from research to manufacturing. During that time he moved from Yorktown to
the Advanced Semiconductor Technology Center in Hopewell Junction NY and
developed the first fully qualified for manufacturing SiGe HBT process. He
then worked on SiGe BiCMOS and moved to Essex Junction Vermont where he
developed the first fully manufacturing qualified SiGe BiCMOS process in a
large volume fabricator.
Dr. Harame now lives in Essex Junction Vermont where he directs IBM’s Microelectronic Division Enablement Area. This area develops both RF/Analog and Digital models and design kits for SOI, CMOS, and SiGe BiCMOS Technologies. David is a Distinguished Engineer of the IBM Corporation. David is the Technical Program Chair for the 2004 IEEE Bipolar BiCMOS Circuits and Technology Meeting. He is also the Lead Symposium Organizer for the 2004 ECS SiGe: Materials, Processes, and Devices Symposium. He has authored or co-authored over 154 articles and holds 16 patents. He is an IEEE Fellow.
Paul A. Kohl, Ph.D., Professor, Department of Chemical Engineering, Georgia Institute of Technology.
Paul A. Kohl is Regents' Professor of chemical engineering at the Georgia Institute of Technology. He received a Ph.D. from The University of Texas at Austin in chemistry in 1978. He was employed at AT&T Bell Laboratories from 1978 to 1989. At Bell Laboratories, he was involved in new materials, analysis, and processing methods for substrate technology, III-V opto-electronic devices, semiconductor devices, and advanced packages.
In 1989, he joined the faculty of the Georgia Institute of Technology, where he is currently a Regents’ Professor. His research interests include ultra low-k dielectric materials, interconnects for microelectronic devices, electronic packaging, and electrochemical energy conversion devices (batteries and fuel cells). He is Editor of the Journal of The Electrochemical Society. He received the Carl Wagner Award from the ECS in 2001. He has over 130 journal publications, and 30 patents.
Yoshio Nishi, Ph.D., Professor
(Research) of Electrical Engineering, Director of Stanford Nanofabrication
Facility, Stanford University.
Dr. Yoshio Nishi is the Director of the
Stanford Nanofabrication Facility and a Research Professor in the
Department of Electrical Engineering at Stanford University. Dr. Nishi
received his B.S. degree in metallurgy from Waseda University in 1962 and
his Ph.D. degree in electronics engineering from the University of Tokyo
in 1973. In 1962 he joined Toshiba Corporation where he worked on silicon
process research and development and pioneered the process simulation for
impurity redistribution in Si-SiO2 systems and also discovery of PB Center
at the Si-SiO2 interface. From 1968 to 1969 he was a Research Associate at
the Stanford Electronics Laboratories, working on high-field transport in
semiconductors and on materials characterization of GaAs liquid phase
epitaxial crystal growth. In 1969 he rejoined Toshiba and supervised the
nonvolatile memory R&D activity working on development of the world's
first MNOS nonvolatile static memories. In 1976 he was responsible for
theoretical and experimental studies of short-channel MOSFETs in the MITI
VLSI project, as well as management of the SOS technology group at
Toshiba. In 1979 he directed work on VLSI process technology, R&D
memory and logic VLSI's. He was responsible for the technical leadership
of memory VLSI R&D, e.g., the world's first CMOS 1Mb dynamic, 256Kb
CMOS static, 1Mb CMOS programmable memories and successfully transferred
to manufacturing.
In 1986 he joined Hewlett-Packard Laboratories as Director of the Silicon Process Laboratory where he built HP's first converged CMOS technology at 0.8 micron geometry used in HP Risc Processor, PA-RISC chip sets. In 1994, he established and became Director of the ULSI Research Laboratory. Dr. Nishi joined Texas Instruments Incorporated in 1995 as Vice President and Director of Research and Development for the Semiconductor Group. In 1996, he was elected Senior Vice President, responsible for R&D activities for digital signal processing solutions, semiconductor processes and devices, memory, as well as components and materials.
Dr. Nishi has published over 125 papers in international technical journals and conferences, and has co-authored nine books. He has been awarded more than 50 patents in the U.S. and Japan. He is a Fellow of the IEEE; a member of the Japan Society of Applied Physics; Institute of Electronics, Communication Engineers of Japan; and the Electrochemical Society. He received the IECE Japan Award in 1972, IR100 awards in 1982 and 1986 for nonvolatile memory productization. In 1995, he received the IEEE Jack A. Morton Award. He is also the 2002 Robert Noyce Medal recipient.
R. Fabian W. Pease, Ph.D., William Ayer Professor of Electrical Engineering, Stanford University.
Dr. Pease is the William Ayer Professor of Electrical Engineering at Stanford
University. His group's areas of research include micro- and nano-fabrication
and their application to electronic and magnetic devices and structures. This
work has included the original demonstration of lithography with the scanning
tunneling microscope, exploring the limits of resolution of deep ultraviolet
lithography, the invention of the micro-channel heat sink and non-conventional
electron beam technology for semiconductor manufacturing.
Dr. Pease served as a radar officer in the Royal Air Force from 1955 to 1957, and received his B.A., M.A., and Ph.D. degrees from Cambridge University in 1960, 1962, and 1964, respectively. His Ph.D. thesis was on High Resolution Scanning Electron Microscopy. After graduating, he was an Assistant Professor of Electrical Engineering at UC Berkeley for three years, where he continued his microscopy research. In 1967, Dr. Pease joined the technical staff of Bell Laboratories, where he first worked on digital television and later led a group that developed the processes for electron beam lithographic mask manufacture, and demonstrated a pioneering LSI circuit built with electron beam lithography. Since 1978 he has been a Professor of Electrical Engineering at Stanford University. On sabbatical in 1993 and 1994, Dr. Pease conducted research on the synthesis of DNA microarrays at Affymetrix Corporation. From 1996 to 1998, he was assigned to the Defense Advanced Research Projects Agency, where he initiated programs in Advanced Microelectronics and in Molecular-Level Printing.
Dr. Pease was appointed the William E. Ayer Professor of Electrical Engineering in March 2001. He is a Fellow of the IEEE, and has served the IEEE in a variety of capacities. He is also a member of the National Academy of Engineering. He has published over 200 articles and authored several book chapters.
T.J. Rodgers is founder,
president, CEO, and a director of Cypress
Semiconductor Corp. He is a
former chairman of the Semiconductor Industry
Association (SIA) and
sits on the board of directors of SolarFlare
Communications, Silicon
Light Machines, Ion America, Silicon Magnetic
Systems, Infinera,
SunPower Corp., and Cypress MicroSystems.
Rodgers was a Sloan scholar at Dartmouth College, where he graduated
as
Salutatorian with a double major in physics and chemistry. He
attended
Stanford University on a Hertz fellowship, earning a master's
degree (1973)
and a Ph.D. (1975) in electrical engineering. At
Stanford, Rodgers invented,
developed, and patented VMOS technology,
which he sold to American
Microsystems Inc. (AMI). He managed the MOS
memory design group at AMI from 1975 to 1980 before moving to Advanced
Micro Devices (AMD), where he ran AMD's SRAM product group. Rodgers was
the founding CEO of Cypress in 1982 and has since built it into an
international integrated circuit supplier with 4,100 employees. Called "a
quintessential entrepreneurial company" by The Wall Street Journal,
Cypress and its management team have received many awards for excellence
in financial management. These include an Encore Award from the Stanford
University Business School as entrepreneurial company of the year in 1988;
an Entrepreneur of the Year award from the global consulting company,
Ernst & Young, in 1991; three Bronze Awards and two Silver Awards from
The Wall Street Transcript for outstanding management; and a Kachina Award
from market-research company In-Stat Inc. for excellence in financial
management.
Rodgers has been cited for his achievements in supporting the
philosophy of
capitalism and freedom, and for his contributions to
philanthropic and other
nonbusiness groups. In 2001, Rodgers received
the Silicon Valley Capitalism
Award for "exemplifying the virtues of
capitalism and defending capitalism
with ethical principles in the
media." Also that year, Rodgers was presented
with an Angel Award by
the International Angel Investors organization for
his venture-capital
activities supporting the semiconductor industry, and
the inaugural
Entrepreneur of the Year Award from the Smith Center for
Private
Enterprise Studies at California State University at Hayward. He
joined
a short list of scholars, including Milton Friedman, in receiving
an
Honorary Degree in Social Sciences from the University of Guatemala
for his
numerous essays on the topics of capitalism and freedom.
Rodgers accepted a Director Award from Vitesse Semiconductor Corp. in 1998
for his contributions to that company as a member of its Board of
Directors between 1987 and 1997. He received an Outstanding Individual
Entrepreneurship Award from the U.S. Association for Small Business and
Entrepreneurship in 1997, and he was named Entrepreneur of the Year in
1986 by the City of Santa Clara, California.
Krishna Saraswat, Ph.D.,
Rickey/Nielsen Professor of Engineering, Stanford University.
He
received his B.E. degree in Electronics in 1968 from the Birla Institute
of Technology and Science, Pilani, India, and his M.S. and Ph.D. degrees
in Electrical Engineering in 1969 and 1974 respectively from Stanford
University, Stanford, CA.
During 1969-70, he worked on microwave transistors at Texas Instruments. Returning to Stanford in 1971, he did his Ph.D. on high voltage MOS devices and circuits. After graduating he joined Stanford University as a Research Associate in 1975 and later became a Professor of Electrical Engineering in 1983. For the next 15 years, Prof. Saraswat worked on modeling of CVD of silicon, conduction in polysilicon, diffusion in silicides, contact resistance, interconnect delay and 2-D oxidation effects in silicon. He pioneered the technologies for aluminum/titanium layered interconnects, CVD of tungsten silicide MOS gates, CVD tungsten MOS gates and tunable workfunction SiGe MOS gates. During the late 80’s he became interested in the economics and technology of single wafer manufacturing. He developed equipment and simulators for single wafer thermal processing, deposition and etching and technology for the in-situ measurements and real-time control. Jointly with Texas Instruments a microfactory for single wafer manufacturing was demonstrated in 1993. Since the mid 90’s Prof. Saraswat has been working on new materials, devices and interconnects for scaling MOS technology to nm range. He has pioneered several new concepts of 3-D ICs with multiple layers of heterogeneous devices. His group has recently demonstrated the first high performance germanium MOSFETs with high-k dielectrics. Since 2000 he has also been doing research on Environmentally Benign Semiconductor Manufacturing and is currently Associate Director of the NSF/SRC Engineering Research Center for it.
Prof. Saraswat has authored or co-authored over 400 technical papers, of which six have received Best Paper Award. He is a Fellow of the IEEE, and a member of both The Electrochemical Society and The Materials Research Society. He received the Thomas Callinan Award from The Electrochemical Society in 2000 for his contributions to the dielectric science and technology. He is the recipient of the 2004 IEEE Andrew Grove Award for seminal contributions to silicon process technology. He received two gold medals for academic excellence during his education in India.
Robert Socha, Imaging Scientist, Technology Development Center, ASML. Dr. Socha received his B.S. degree in electrical engineering from University of Michigan in 1991 and his Ph.D. degree in electrical engineering from the University of California at Berkeley in 1997. At the University of California at Berkeley, his studies concentrated on optical lithography under the direction of Prof. Andrew Neureuther. In 1997, he joined National Semiconductor and worked on optical lithography resolution enhancement techniques such as optical proximity correction (OPC) and phase shift mask (PSM). In 1999 he joined ASML where he works with customers to help them use ASML lithography equipment more effectively. Dr. Socha uses various resolution enhancement techinques to achieve the smaller resolution. These resolution enhancement techniques include mask OPC, phase shift mask, off axis illumination, and mask-illumination optimization. In addition to helping customers with resolution enhancement techniques, Dr. Socha also uses his background in modeling and coding to produce resolution enhancement software with ASML Masktools.
Dr. Socha has published 25 papers in international technical journals and conferences, and is currently working on a book for mask resolution enhancement techniques. He has been awarded 5 patents internationally. He is a member of SPIE and a member of the IEEE. In 1992 he was awarded a National Science Foundation Graduate Fellowship and in 1996 he was awared a Semiconductor Research Corporation Graduate Fellowship.
