Semiconductor Devices and Manufacturing

The Institute online program on Semiconductor Devices and Manufacturing covers various topics of significant interest in modern semiconductor integrated circuits with emphasis on the state-of-the-art silicon integrated circuit devices, process integration, and manufacturing technologies. This online offering is a series of nine short courses by Stanford faculty as well as leading experts from other universities and industry.

• 3-Dimensional ICs: Motivation, Performance Analysis and Technology
• Chip Packaging Technologies
• Microelectronics to Nanoelectronics
• Microlithography
• Nanoelectronics: Electrons in Reduced Dimensions and Future Devices
• Process Integration Strategies: 90 nm in 2004 to 30 nm in 2010
• Resolution Enhancement Techniques for Optical Lithography
• RF-CMOS and SiGe-BiCMOS Technologies for RF Analog and Mixed-Signal Integrated Circuits
• SOI Devices and Technology
  

3-Dimensional ICs: Motivation, Performance Analysis and Technology
Krishna Saraswat – Ph.D., Professor of Electrical Engineering, Stanford University

This course analyzes the limitations of the current interconnect technologies & designs and presents 3-D design strategies to alleviate these constraints and to facilitate SoC applications. We show that by partitioning a planar chip into stacked blocks, each occupying a separate level linked by vertical interconnects, significant improvement in performance and reduction in wire-limited chip area is achieved. It is shown that heat sinking advancements will be necessary for reliable 3-D ICs. We also cover the 3-D IC fabrication technologies, modeling, and applications.
(172 minutes)

Chip Packaging Technologies
Paul Kohl – Ph.D., Professor of Chemical and Biomolecular Engineering, Georgia Institute of Technology

Packaging has evolved from being a simple method of making electrical connections to a vital part of the system. The drive toward higher power and faster chips has placed enormous demands on the electrical, mechanical, size, and heat transfer capabilities of the package and the mounting substrate. This course discusses the driving forces and technologies for chip packaging and evolution of the technology. We describe technologies for wafer-scale and chip-scale packaging. High-density substrates and their contribution to chip packaging are presented. We conclude with a review of the emerging packaging trends.
(203 minutes)

Microelectronics to Nanoelectronics
Prof. Yoshio Nishi – Ph.D., Professor of Electrical Engineering, Stanford University

As integrated circuits keep scaling down, following the Moore's Law and scaling principles, microelectronics is quickly moving into the nanoelectronics regime. This course explains this transition, its implications, as well as the challenges and opportunities. We present MOS device physics and technology with emphasis on nano-devices, and the nanoelectronics interconnects. Additional discussions cover the role of new materials for the future of nano-scale chips, on-chip interconnect / technology evolution, and emerging opportunities.
(203 minutes)

Microlithography
Prof. Fabian Pease – Ph.D., Professor of Electrical Engineering, Stanford University

Microlithography is the key technology pacing the advance of Moore's Law. This course presents an overview of various microlithography technologies for modern semiconductor IC manufacturing. The course describes state-of-the-art optical lithography technologies which continue to be the manufacturing choice. Since both the wafer exposure tools and the masks are becoming uneconomically expensive for many applications, alternatives are being considered. This course also covers electron and extreme ultraviolet radiation, mechanical printing, and maskless exposure tools.
(189 minutes)

Nanoelectronics: Electrons in Reduced Dimensions and Future Devices
David Goldhaber-Gordon – Ph.D., Assistant Professor of Physics, Stanford University

This course discusses quantum effects in the sub-100nm nanoelectronics regime, along with strategies to take advantage of those effects in designing novel electronic devices. Such effects include: electron-electron interaction, tunneling, confinement, and spin-orbit coupling. Related nano-devices include: scaled FET, resonant tunneling diode, single-electron transistor, and spin transistors. We present strategies for fabrication of complex circuits, choice of materials for nano-devices, CMOS integration, and computer architectures based on novel devices.
(167 minutes)

Process Integration Strategies: 90 nm in 2004 to 30 nm in 2010
Dennis Buss – Ph.D., Vice President, Texas Instruments

This course reviews the industry mega-trends, including SOC for personal Internet products, transistor leakage, voltage scaling limits, proliferation of CMOS, and limits to scaling. Process integration strategies for MOSFETs are presented for Moore’s Law scaling through 2010. We describe planar bulk CMOS, comprising strain, high-K/metal gates, and shallow junctions. These technologies are placed in an 8-year strategy and contrasted with planar SOI. The transition to multi-gate transistors and process Integration vs. product strategies are explained.
(211 minutes)

Resolution Enhancement Techniques for Optical Lithography
Robert Socha, Imaging Scientist, Technology Development Center, ASML

As optical lithography is pushed to print sub-wavelength features, the
ultimate resolution limit can be achieved by using enhancement techniques.
These enhancement techniques lower the k1 factor. The k1 factor is defined
by half-pitch resolution equals k1l/NA in which k1=0.25 is the fundamental
limit on half-pitch resolution. The k1 factor is reduced by optimizing the
entire lithography process which includes the IC design, the mask, the
scanner, and the photoresist. At low k1, the entire lithography process is
a coupled problem in which changing one part of the four parts of the
process affects other parts of the process. In order to achieve the lowest
k1 possible in production, understanding the effect of each part of the
lithography process on imaging is essential.
(201 minutes)

RF-CMOS and SiGe-BiCMOS Technologies for RF Analog and Mixed-Signal Integrated Circuits
David Harame, Director Semiconductor Technologies Enablement, IBM

This course presents RF-CMOS and SiGe-BiCMOS as RF/Analog and Mixed-Signal Circuit technologies. We introduce the wireless and wired applications and their requirements. We describe RF-CMOS and the CMOS device performance for RF applications. SiGe-BiCMOS technology and device design are explained. The advantages and the disadvantages of each technology are presented. We also cover passives, which are important components of RF/Analog technology, and conclude with a discussion on the RF/Analog enablement.
(153 minutes)

SOI Devices and Technology
Jean-Pierre Colinge - Ph.D., Professor of Electrical Engineering, University of California, Davis

SOI CMOS is now used for mainstream microprocessors, low-voltage, and mixed-mode circuits. SOI offer superior performance compared to bulk CMOS and enable the ITRS roadmap down to the 22nm node. This course starts with a history of SOI materials, devices and circuits. We describe the modern SOI materials as well as SOI CMOS technologies applications. The device physics for partially and fully depleted MOSFETs are described. We present advanced SOI MOSFETs (double/triple-gate devices, DTMOS) and modern SOI CMOS processing.
(212 minutes)